The invention relates to a threshold circuit arrangement and to a method for operating a threshold circuit arrangement.
In semiconductor devices, in particular e.g., in corresponding integrated (analog or digital) computing circuits and/or semiconductor memory devices, as well as other electric circuits or—to put it more general—signal processing systems, threshold circuit arrangements, e.g., appropriate comparators, are frequently used.
Conventional comparators may, for instance, each include one or a plurality of operational amplifiers and compare, e.g., a signal present at a plus (or minus) input of the respective comparator with a signal (threshold) present at a minus (or plus) input of the comparator.
If the signal present at the plus input of a corresponding comparator is larger than the signal present at the minus input, the respective comparator outputs a comparator output signal having a first level, in particular a logic high level, and otherwise a comparator output signal having a second level differing from the first level, in particular a logic low level.
Furthermore, comparators including a hysteresis are known, e.g., Schmitt triggers.
In the case of a Schmitt trigger—due to the hysteresis—switch on and switch off levels come apart: If the level of a signal present at an input of the Schmitt trigger rises above a first, predetermined input level value (first threshold), the Schmitt trigger outputs an output signal having a first output level, in particular a logic high level. Only when the level of the signal present at the input of the Schmitt trigger drops below a second, predetermined input level value (second threshold) that is lower than the above-mentioned first input level value, does the output level of the output signal output by the Schmitt trigger change from the above-mentioned first output level to a second level differing from the first output level (in particular to a logic low level).
Thus, it is prevented that noise-afflicted input signals result in a frequent switching of the comparator.
Conventional comparators with and without hysteresis are, for instance, described in U. Tietze, Ch. Schenk, 9th edition 1990, pages 180-185.
The comparators known in prior art include, i.a., the disadvantage that it is not only signals that—like e.g., the first input signal (“input signal 1”) illustrated in FIG. 1—rise relatively quickly and exceed a corresponding threshold relatively strongly and for a relatively long time (e.g., the threshold Ref 2 illustrated in FIG. 1) result in a switching of the comparator, but also signals that—like e.g., the second and third input signals (“input signal 2” or “input signal 3”) illustrated in FIG. 1—rise relatively slowly and/or exceed the threshold Ref 2 only relatively weakly and/or for a relatively short time only.
The consequence of this is that the output signal output by the comparator (e.g., the output signal OUT illustrated in FIG. 1) possibly changes its state relatively late only (e.g., in reaction to the above-mentioned second input signal (“input signal 2”) only at a point in time T2, or e.g., in reaction to the above-mentioned third input signal (“input signal 3”) only at a point in time T3), i.e. afflicted with relatively strong delays and/or for a relatively short time only (e.g., with the above-mentioned second input signal (“input signal 2”) only for a duration ΔT2, or e.g., with the above-mentioned third input signal (“input signal 3”) only for a duration ΔT3).
For these and other reasons, there is a need for the present invention.